logic gate
英 [ˈlɒdʒɪk ɡeɪt]
美 [ˈlɑːdʒɪk ɡeɪt]
n. 逻辑门，逻辑闸(以两种方式之一对所输入数据进行输出的电子开关)
牛津词典
noun
- 逻辑门，逻辑闸（以两种方式之一对所输入数据进行输出的电子开关）
an electronic switch that reacts in one of two ways to data that is put into it. A computer performs operations by passing data through a very large number of logic gates .
英英释义
noun
- a computer circuit with several inputs but only one output that can be activated by particular combinations of inputs
双语例句
- Based on the I-U characteristics of single-electron transistor ( SET) and the concepts of CMOS digital circuits design, a sort of logic gate is proposed.
基于单电子晶体管（SET）的I＿U特性和CMOS数字电路设计思想，提出了一类互补型SET逻辑门。 - The special Flip-Flop, combination logic gate and improved topology of Prescaler, enable the Prescaler to intensify the low power-high speed tradeoff.
其中，采用了特殊的D触发器和组合逻辑门结构，改进了预置数分频器结构，能够使分频器工作在低功耗、高速度之间有比较好的折衷。 - Within this context, the first chapter indicates quantum logic gate and the second chapter demonstrates composing and running of the quantum C-NOT gate.
本文第一章介绍了量子逻辑门，第二章介绍了量子C-NOT门的构成及运行，第三章和第四章是具体的研究工作。 - And a computer inside actually assembles with many digital circuits, while digital circuits can be seen as the logic gate network that achieve by the electronic devices.
而一台电子计算机的内部实际上是由许许多多个数字电路组成，而数字电路可以看作是用电子器件实现的逻辑门网络。 - Use the quantum logic gate for implementing multi-purpose quantum cloning machine.
利用通用量子门实现多用途量子克隆机的方案。 - Diode transistor logic gate
二极管晶体管逻辑门 - Since any logic gate can be constructed by two-qubit controlled not gates ( CN gate) and one qubit rotation gate ( R gate), the realization of the CN and R gates has been studied extensively.
任意量子门都可以由二比特控制非门（CN门）和单比特旋转门（R门）组成。因此，人们致力于研究如何实现CN门和R门。 - In theory, the molecular logic gate based on DNA is considered as fundamental unit of both DNA computer architecture and implement.
理论上来说，基于DNA的分子逻辑门是DNA计算机体系结构的产生基础和DNA计算机实现技术的硬件基础。 - Based on the dual-rail logic, a cascadable parallel binary logic gate was, proposed.
基于双轨逻辑，本文提出一种可级联的并行二值逻辑门。 - After study a series array multipliers algorithms and architectures,. the author design a high-performance multiplier in logic gate level, which using Booth and Wallace skill.
本文研究讨论了各种不同阵列乘法器的结构和原理，并完成了在门电路级设计了32位基4Booth编码并采用42压缩的Wallace高性能阵列乘法器电路。